Scan tests are well known as a method of testing semiconductor devices (LSIs: Large-Scale Integrated devices). FIG. 1 illustrates an example of the configuration of an LSI having scan test functions. The LSI in this figure has combinational circuits c1 to c8 comprising a plurality of circuit elements which executes data processing and computation, and scan flip-flops sf1 to sff connected to the combinational circuits c1 to c8. The scan flip-flops (hereafter “FFs”) sf1 to sff have multiplexer functions.
Further, the LSI of FIG. 1 has a user mode during normal operation, and a scan mode during scan testing. In the case of the user mode, the combinational circuits c1 to c8 together with the scan flip-flops sf1 to sff perform processing of data input from an input terminal UI, and output the processing result to an output terminal UO.
On the other hand, in the case of the scan mode, a scan-in terminal SI and scan-out terminal SO are connected in series to form a scan chain. A user inputs a data pattern from the scan-in terminal SI, and the data can be set in the scan FFs sf1 to sff as arbitrary input values to the combinational circuits c1 to c8. Further, by shifting a scan chain, the user can cause a value indicating the result of processing of the combinational circuits c1 to c8, held by the scan FFs sf1 to sff, to be output from the scan-out terminal SO. By validating the data pattern output, the user can judge whether the processing of the combinational circuits c1 to c8 has been performed appropriately.